1. Field of the Invention
The present invention is generally in the field of semiconductor chips. More specifically, the invention is in the field of capacitors used in semiconductor chips.
2. Background Art
High performance CMOS and BiCMOS mixed signal and RF circuits require integrated capacitors with precision control of capacitor values and good capacitor matching, along with high reliability, low defect density, a high quality factor (xe2x80x9cQxe2x80x9d), and low parasitic capacitance.
Metal-insulator-metal (xe2x80x9cMIMxe2x80x9d) capacitors have been successfully integrated into an existing multi-level metallization process used in the fabrication of integrated mixed signal and RF circuits on semiconductor chips. When MIM capacitors are fabricated at the second metallization layer or higher, parasitic capacitance is reduced due to the increased distance of the capacitor from the substrate. In addition, the quality factor of MIM capacitors, i.e. the ratio of stored energy to dissipated energy, is higher than conventional poly-poly and metal-poly capacitors due to the lower resistance of the top and bottom plates of the MIM capacitor.
In addition to the benefits of MIM capacitors described above, more precise control of capacitor values, as well as better capacitor matching and lower defect density of capacitor dielectrics have been realized through the utilization of various MIM capacitor fabrication techniques. However, due to their importance in semiconductor applications, device engineers are continually looking for ways to further improve these capacitor characteristics.
A number of semiconductor applications require accurate xe2x80x9cmatchingxe2x80x9d of capacitors. Capacitors are matched if their absolute values can be determined and replicated with accuracy. In addition, efforts have been made to further reduce the defect density of capacitor dielectrics. Defect density refers to the number of defects within a defined area of the capacitor dielectric, for example, defects/cm2 of the capacitor dielectric. A high defect density in a capacitor dielectric leads to problems such as shorted capacitors, higher leakage current, i.e. undesired current flow through the capacitor, and lower breakdown voltage, i.e. the voltage applied to the capacitor at which the capacitor dielectric no longer acts as an insulator, and thus reduces the long-term reliability of the capacitor.
FIG. 1 shows a cross section of conventional MIM capacitor 100 fabricated on a semiconductor die. Dielectric 106 is shown situated between top plate 108 and bottom plate 104. Bottom plate 104 rests on top of a first inter-layer dielectric (xe2x80x9cILDxe2x80x9d) 102 which in turn rests on a metal layer or a semiconductor substrate (not shown in FIG. 1). Top plate 108 can be made of conductive material such as titanium nitride while bottom plate 104 can be made of a different conductive material such as an aluminum-copper alloy. Dielectric 106 is typically made of silicon nitride or silicon oxide, while ILD 102 is typically silicon oxide.
A known process flow of MIM capacitor fabrication begins with the deposition of an interconnect metal layer on top of a first inter-layer dielectric. A thin layer of capacitor dielectric film is then deposited on top of the interconnect metal layer. Another metal layer is then deposited on top of the capacitor dielectric. A top plate is then patterned and etched out of the top metal layer with an etch chemistry selective to the top plate metal. Etch stop is used on the capacitor dielectric film to prevent etching of the capacitor dielectric film during this step. This top plate functions as a first electrode of the MIM capacitor.
A bottom plate is subsequently patterned and etched to form a second electrode of the MIM capacitor. During this step, residual capacitor dielectric film, i.e. all of the layer of capacitor dielectric film except that portion that will be between the top plate and bottom plate of the capacitor, is first etched away, followed by the etching of the bottom plate. The photoresist used to define the patterning of the bottom plate is then removed using dry etch, wet etch, or a combination of both. Subsequent to the patterning and etching of the bottom plate of the capacitor, a second layer of ILD (not shown in FIG. 1) is deposited on top of the first layer of ILD and surrounds the MIM capacitor comprising the top plate, capacitor dielectric, and bottom plate. This second ILD layer can also be silicon oxide.
It is well-known that the capacitance value between the two plates of a parallel plate capacitor, such as the MIM capacitor shown in FIG. 1, is calculated by the equation:                               C          a                =                                            ϵ              0                        ⁢                          ϵ              r                        ⁢            A                    t                                    (                  Equation          ⁢                      xe2x80x83                    ⁢          1                )            
where xcex50 is the permittivity of the free space (xcex50=8.85xc3x9710xe2x88x9214 F/cm), xcex5r is the relative permittivity (also referred to as the dielectric constant or xe2x80x9ckxe2x80x9d), A is the surface area of plate 104 (or plate 108) and t is the thickness of dielectric layer 106. In addition to the area component as given by Ca above, a parasitic perimeter component also exists. The parasitic perimeter capacitance is obtained from the fringing fields between the edges of the top and bottom plates of the capacitor. Thus, the total capacitance may be expressed as
C=ACA+PCPxe2x80x83xe2x80x83(Equation 2)
where CA=capacitance per unit area =Ca/A, Cp=perimeter capacitance per unit length, and P=perimeter of the capacitor (or perimeter of plate 104 or 108).
Given the capacitance Equation 1, it can be seen that the value of the capacitance is proportional to the dielectric constant of the capacitor""s dielectric. Variations in the dielectric constant of the capacitor dielectric, such as capacitor dielectric 106, result in variations in the capacitance value and thus makes matching of capacitors difficult. In addition to the relation of the capacitor dielectric to capacitor matching, many other important characteristics of the capacitor are dependent on the capacitor dielectric. As discussed above, defects or voids in the capacitor dielectric result in an increased leakage current through the capacitor. Also, the breakdown voltage of the capacitor is a function of the strength and defect density of the capacitor dielectric.
As a result of the dependency on the capacitor dielectric of such important characteristics of the capacitor as capacitance matching, breakdown voltage, and leakage current, device engineers wish to maintain the integrity of the capacitor dielectric during the semiconductor die fabrication process to ensure that the desired characteristics of the capacitor will be preserved.
However, an undesired byproduct of the known MIM capacitor formation process described above is the undercutting of the capacitor dielectric along the perimeter sidewalls of the capacitor dielectric. This not only affects the value of the capacitor, but may also weaken the dielectric at the edge of the capacitor due to voids and defects, thus increasing the leakage current as well as reducing the breakdown voltage of the capacitor. This capacitor dielectric undercutting is a result of the attack of the exposed dielectric along the perimeter of the capacitor during subsequent etching and patterning of bottom plate 104 of the MIM capacitor, as discussed below.
Dry etch fluorinated chemistries such as nitrogen trifluoride (xe2x80x9cNF3xe2x80x9d), carbon terafluoride (xe2x80x9cCF4xe2x80x9d) and sulphur hexafluoride (xe2x80x9cSF6xe2x80x9d), are commonly used in MIM capacitor formation to strip the photoresist after etching the bottom plate of the capacitor from the interconnect metal layer. These etch chemistries attack the capacitor dielectric at the perimeter sidewalls of the capacitor as the perimeter of the capacitor becomes to completely exposed during the bottom plate photoresist strip process. Subsequent wet strips to remove polymers after etching the bottom metal and stripping the resist may also attack the perimeter sidewall in a similar fashion. The result is shown in expanded views 101 and 105 in FIG. 1. After the bottom plate metal etch step, the perimeter sidewalls of capacitor dielectric 106 have been cut back from their original extensions indicated by dashed lines 103 and 107 in expanded views 101 and 105. As such, the perimeter sidewalls of capacitor dielectric 106 and are no longer flush with top plate 108, as shown in expanded views 101 and 105. In addition, the conducting by-products during the dry strip and/or wet strip may impinge on the exposed sidewall of the dielectric causing current leakage paths between the two plates of the capacitor.
As a result of this undercutting of the capacitor dielectric by the etch chemistry used to etch bottom plate 104, voids are created along the perimeter sidewalls of the capacitor. These voids between the top and bottom metal plates will have a different dielectric constant than the remainder of the dielectric material between the top and bottom plates of the capacitor, i.e. the dielectric constant of the voids will essentially be that of the air. Thus, the capacitance value as determined by Equation 1 will vary based on the amount of undercutting of the capacitor dielectric during the bottom plate metal etch step. Therefore, capacitor matching will be very difficult to control because varying capacitor values of different capacitors on the semiconductor die will result based on varying degrees of capacitor dielectric undercutting.
In addition to the difficulty of accurate capacitor matching, voids and defects along the perimeter sidewalls of the capacitor dielectric will result in long term reliability problems such as increased leakage current and a lower breakdown voltage for the capacitor.
Thus it is seen that a reliable MIM capacitor fabrication process is needed that will ensure that the integrity of the capacitor dielectric will be maintained during the resist stripping step and during the patterning of the bottom plate metal, thus ensuring more precise control of capacitor values, accurate capacitor matching of capacitors on the semiconductor die, and improved long-term reliability of the capacitors.
The present invention is directed to method for fabrication of an MIM capacitor and related structure. The invention is a reliable MIM capacitor fabrication process that ensures that the integrity of the capacitor dielectric is maintained during subsequent process steps, thus ensuring more precise control of capacitor values, accurate capacitor matching of capacitors on the semiconductor die, and improved long-term reliability of the capacitors.
According to one embodiment of the invention, an interconnect metal layer is deposited. The interconnect metal layer can be, for example, aluminum, copper, or an aluminum-copper alloy. Then a first dielectric is fabricated over the interconnect metal layer. The first dielectric can be, for example, silicon nitride, tantalum pentooxide, or silicon oxide. A top metal layer is then formed over the first dielectric. The top metal layer can be, for example, titanium nitride, tantalum nitride, aluminum or a composite stack of these materials.
Next, the top metal layer and the first dielectric are patterned and etched to form a capacitor first electrode and a capacitor dielectric. Thereafter a layer of a second dielectric is deposited over the capacitor first electrode and the capacitor dielectric. The second dielectric can be, for example, silicon oxide. Then the second dielectric is etched back, as a result of which spacers covering common sidewalls of the capacitor first electrode and the capacitor dielectric are formed. The spacers protect the capacitor dielectric from being etched during subsequent processing steps. In one embodiment, the invention is a structure fabricated according to the process steps discussed above.